FIGS. 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device.
As shown in FIG. 1A, lower metal wire 18 is formed passing through capping layer 10, interlayer dielectric film 12 and first etch stop film 14. First interlayer dielectric films 16 are formed on and/or over both sides of lower metal wire 18. Capping layer 10 is provided for preventing horizontal diffusion of lower metal wire 18. Second interlayer dielectric film 22 composed of a low dielectric material, second etch stop layer 24 and third interlayer dielectric film 26 made of a low dielectric material are stacked sequentially on and/or over lower metal wire 18 and first interlayer dielectric film 16. Novolac 28 is buried in a via hole formed in interlayer dielectric films 22 and 26 and second etch stop film 24.
As shown in FIG. 1B, a blanket etching is performed to remove a portion of novolac 28 such that another portion of novolac 28A remaining in the via hole. Photoresist pattern 32 is formed on and/or over third interlayer dielectric film 26 and an etching is then performed using photoresist pattern 32 as a mask, thereby forming a trench between third interlayer dielectric film patterns 26A and a via hole. Novolac 28 is not completely buried in the via hole due to the defects generated in burying novolac 28 caused by a gas condensation, coating of novolac 28 or particles flowed during ashing, such that novolac 28 may generate void 30. As shown in FIG. 1B, while the trench is formed, capping layer 20 fails to endure and thus is broken or removed to expose lower metal wire 18 such that oxidation 34 of the exposed copper metal wire 18 may be caused.
As shown in FIG. 1C, when upper metal wire 38 is buried in the trench and via hole, a problem arises in that copper void 36 is caused by corrosion between upper metal wire 38 and lower metal wire 18. Accordingly, since a general dual damascene process forms a via hole and a trench using novolac 28, capping layer 20 is broken or removed so that oxide film 34 (CuO/Cu2O) is formed on and/or over lower metal wiring composed of copper 18 and at the exposed interface between a via and lower metal wire 18. Thereby, a phenomenon of fatal copper corrosion and copper void(s) results. This in turn, causes a problem in reliability such as an earlier defect and stress migration (SM)/electro migration (EM) of a device.